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target 64m ddr sgram - 1 - KM432D2131 rev. 0.3 (may. 1999) 64mbit ddr sgram revision 0.3 may 1999 512k x 32bit x 4 banks with bi-directional data strobe double data rate synchronous graphic ram samsung electronics reserves the right to change products or specification without notice. www..net
target 64m ddr sgram - 2 - KM432D2131 rev. 0.3 (may. 1999) revision history revision 0.3 (may 1999) ? corrected trdl related typo. revision 0.0 (december 1998) - target spec ? defined target specification
target 64m ddr sgram - 3 - KM432D2131 rev. 0.3 (may. 1999) the KM432D2131 is 67,108,864 bits of hyper synchronous data rate dynamic gram organized as 4 x 524,288 words by 32 bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 1.328gb/s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. ? 3.3v 5% power supply for device operation ? 2.5v 5% power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 2, 3 (clock) -. burst length (2, 4, 8 and full page) -. burst type (sequential & interleave) ? full page burst length for sequential burst type only ? start address of the full page burst should be even ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? data i/o transactions on both edges of data strobe ? data input & output & dm are synchronized with dqs general description features ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 16ms refresh period (2k cycle) ? 100pin tqfp package ? maximum clock frequency up to 166mhz ? maximum data rate up to 333mbps/pin graphics features ? smrs cycle. -. load color register ? 16 columns block write. ? byte masking with dm for block write operation is sup- ported. for 512k x 32bit x 4 bank ddr sgram 512k x 32bit x 4 banks double data rate synchronous graphic ram with bi-directional data strobe ordering information part no. max freq. max data rate interface package KM432D2131tq-g6 166mhz 333mbps/pin sstl 100 tqfp KM432D2131tq-g7 143mhz 286mbps/pin KM432D2131tq-g8 125mhz 250mbps/pin KM432D2131tq-g0 100mhz 200mbps/pin
target 64m ddr sgram - 4 - KM432D2131 rev. 0.3 (may. 1999) pin configuration (top view) pin description ck, ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 10 address input cs chip select dq 0 ~ dq 31 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq s dqs data strobe v ssq ground for dq s dmi data mask dsf define special function rfu reserved for future use mcl must connect low dq29 vssq dq30 dq31 vss vddq n.c n.c n.c n.c n.c vssq rfu dqs vddq vdd dq0 dq1 vssq dq2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 d q 3 v d d q d q 4 d q 5 v s s q d q 6 d q 7 v d d q d q 1 6 d q 1 7 v s s q d q 1 8 d q 1 9 v d d q v d d v s s d q 2 0 d q 2 1 v s s q d q 2 2 d q 2 3 v d d q d m 0 d m 2 w e c a s r a s c s b a 0 b a 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 a7 a6 a5 a4 vss a9 n.c n.c n.c n.c n.c n.c n.c n.c a10 vdd a3 a2 a1 a0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 100 pin tqfp 20 x 14 mm 2 0.65 mm pin pitch d q 2 8 v d d q d q 2 7 d q 2 6 v s s q d q 2 5 d q 2 4 v d d q d q 1 5 d q 1 4 v s s q d q 1 3 d q 1 2 v d d q v s s v d d d q 1 1 d q 1 0 v s s q d q 9 d q 8 v d d q v r e f d m 3 d m 1 c k c k c k e d s f , m c l a 8 ( a p ) 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1
target 64m ddr sgram - 5 - KM432D2131 rev. 0.3 (may. 1999) input/output functional description *1 : the timing reference point for the differential clocking is the cross point of ck and ck . for any applications using the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq s and dm s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicates the power down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras input latches row addresses on the positive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. dqs input/output data input and output are synchronized with both edge of dqs. dm 0 ~ dm 3 input data in mask. data in is masked by dm latency=0 when dm is high in burst write. dm 0 for dq 0 ~ dq 7, dm 1 for dq 8 ~ dq 15, dm 2 for dq 16 ~ dq 23, dm 3 for dq 24 ~ dq 31. dq 0 ~ dq 31 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 10 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 10 , column addresses : ca 0 ~ ca 7 . column address ca 8 is used for auto precharge. v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. dsf, mcl define special function enables block write and special mode register set and must be con- nected low to disable these special functions.
target 64m ddr sgram - 6 - KM432D2131 rev. 0.3 (may. 1999) block diagram (512kbit x 32i/o x 4 bank) bank select timing register a d d r e s s r e g i s t e r r e f r e s h c o u n t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r data input register serial to parallel 512kx32 512kx32 512kx32 512kx32 s e n s e a m p 2 - b i t p r e f e t c h o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register s t r o b e g e n . ck, ck add lcke ck, ck cke cs ras cas we dmi ldmi ck, ck lcas lras lcbr lwe lwcbr l r a s l c b r ck, ck 64 64 32 32 lwe ldmi x32 dqi data strobe dsf intput buffer color register mux block write control
target 64m ddr sgram - 7 - KM432D2131 rev. 0.3 (may. 1999) ? power-up sequence ddr sgrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and start clock. must maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200 us . 3. issue precharge commands for all banks of the device. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. cf) sequence of 4 & 5 is regardless of the order. functional description power up sequence & auto refresh(cbr) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp minimum of 2 refresh cycles are required 1 tck precharge all bank 2nd auto refresh mode register set any command t rc 1st auto refresh t rc ck, ck inputs must be stable for 200 us ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
target 64m ddr sgram - 8 - KM432D2131 rev. 0.3 (may. 1999) the mode register stores the data for controlling the various operating modes of ddr sgram. it programs cas latency, addressing mode, burst length, test mode and various vendor specific options to make ddr sgram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the ddr sgram. the mode register is written by asserting low on cs , ras , cas and we (the ddr sgram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 10 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. one clock cycle is requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 7 , a 8 , ba 0 and ba 1 must be set to low for normal ddr sgram operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. mode register set(mrs) address bus mode register cas latency a 6 a 5 a 4 latency 0 0 0 reserve 0 0 1 reserve 0 1 0 2 0 1 1 3 1 0 0 reserve 1 0 1 reserve 1 1 0 reserve 1 1 1 reserve burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve a 7 mode 0 normal 1 test burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. ck, ck precharge nop nop mrs nop nop nop 2 0 1 5 3 4 8 6 7 any nop all banks command t rp t mrd =1 t ck ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu tm cas latency bt burst length
target 64m ddr sgram - 9 - KM432D2131 rev. 0.3 (may. 1999) define special function(dsf) the dsf controls the graphic applications of sgram. if dsf is tied to low, sgram functions are the same as sdram functions. sgram can be used as an unified memory by the appropriate dsf command. all the graphic function mode can be entered only by setting dsf high when issuing commands which otherwise would be normal sdram commands. see the sessions below for the graphic functions that dsf control. special mode register set(smrs) there is a special mode register in ddr sgram. it is color register. this usage will be explained at "block write" session. when a6 and dsf goes high in the same cycle as cs , ras , cas and we going low, load color register(lcr) process is executed and the color register is filled with color data for associated dq s through the dq pins. at the next clock of lcr, a new commands can be issued. smrs, compared with mrs, can be issued at the active state under the condition that dq s are idle. special mode register programmed with smrs address ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 function x lc x load color register a 6 function 0 disable 1 enable command smrs cycle smrs nop nop nop nop nop nop dqs dq s color ck, ck 2 0 1 5 3 4 8 6 7 nop nop load color register block write is a feature allowing the simultaneous writing of consecutive 16 columns of data within a ram device during a single access cycle. during block write the data to be written comes from an internal "color" register. the block of col- umn to be written is aligned on 16 column boundaries and is defined by the column address with the 4 lsb s ignored. write command with dsf=high enables block write for the associated bank. a write command with dsf=low enables normal write for the associated bank. the block width is 16 column where column="n" bits for by "n" part. the color reg- ister is the same width as the data port of the chip. the color register provides the data without column masking. so dq states are don t cared. and null column mask command with high state on dqs make no problem. dqs should toggle once for valid data mask(dm) input. block writes are always non-burst, independent of the burst length that has been programmed into the mode register. back to back block writes are allowed provided that the specified block write cycle time(tbwc) is satisfied. block write t smrd =1 t ck
target 64m ddr sgram - 10 - KM432D2131 rev. 0.3 (may. 1999) t cdlw=0 note 2 1. t ccd : cas to cas delay. (=1 tck) 2. t cdlw : last data in to new column address delay. (=0 tck) 3. t bwc : block write minimum cycle time. (=1 tck) t cdlw=0 note 2 t bwc note 3 2) write interrupted by block write (bl=2) 3) block write to block write ck, ck cmd add ck, ck cmd add dq *note : 1) block write to precharge 4) byte masking for block write ck, ck cmd dmi dq ck, ck cmd t bpl bw pre wr wr wr bw t ccd note1 t ccd note1 a b c d bw bw a b smrs 16 col. bw write 16 col. bw byte masking for block write byte masking for normal write color 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 dqs din 0 din 1 din a 0 din a 1 din b 0 din b 1 din c 0 din c 1 t bpl pre
target 64m ddr sgram - 11 - KM432D2131 rev. 0.3 (may. 1999) burst mode operation is used to provide a constant flow of data to memory locations(write cycle), or from memory loca- tions(read cycle). there are two parameters that define how the burst mode operates. these parameters including burst sequence and burst length are programmable and determined by address bits a 0 ~ a 3 during the mode register set com- mand. the burst type is used to define the sequence in which the burst data will be delivered or stored to the sgram. two types of burst sequences are supported, sequential and interleaved. see the below table. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to have values of 2, 4, 8 or full page. for the full page operation, the starting address must be an even number. burst mode operation burst length and sequence burst length starting address(a 2 , a 1 , a 0 ) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the ddr sgram has four independent banks, so two bank select addresses(ba 0 , ba 1 ) are supported. the bank activation command must be applied before any read or write operation is executed. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time(t rcd min ). once a bank has been activated, it must be precharged before another bank activation command can be applied to the same bank. the minimum time interval between interleaved bank activation commands(bank a to bank b and vice versa) is the bank to bank delay time(t rrd min ). bank activation command address command ras - cas delay( t rcd ) bank activation command cycle ( cas latency = 2) bank a row addr. bank a col. addr. bank a activate write a with auto nop precharge ras - ras delay time( t rrd ) bank a row addr. bank b row. addr. bank a activate bank b activate nop row cycle time( t rc ) n n+1 n+2 2 0 1 : don t care ck, ck
target 64m ddr sgram - 12 - KM432D2131 rev. 0.3 (may. 1999) burst read operation in ddr sgram is in the same manner as the current sdram such that the burst read command is issued by asserting cs and cas low while holding ras and we high at the rising edge of the clock after t rcd from the bank activation. the address inputs (a 0 ~a 7 ) determine the starting address for the burst. the mode register sets type of burst( s equential or interleave) and burst length(2, 4, 8, full page). the first output data is available after the cas latency from the read command, and the consecutive data are presented on the falling and rising edge of data strobe adopted by ddr sgram until the burst length is completed. burst read operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. there is no real write latency required for burst write cycle. the first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after t dqss from the rising edge of the clock that the write command is issued. the remaining data inputs must be supplied on each subse- quent falling and rising edge of data strobe until the burst length is completed. when the burst has been finished, any additional data supplied to the dq pins will be ignored. burst write operation command < burst length=4, cas latency=2, 3 > read a nop nop nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 dqs dq s cas latency=3 dout 0 dout 1 dout 2 dout 3 command < burst length=4 > nop write nop nop nop nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 t dqss 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 ck, ck ck, ck t dshz t sdqs t acs t shz t slz preamble postamble preamble postamble
target 64m ddr sgram - 13 - KM432D2131 rev. 0.3 (may. 1999) a burst read can be interrupted before completion of the burst by new read command of any bank. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point the data from the interrupting read command appears. read to read interval is minimum 1 tck. burst interruption read interrupted by a read to interrupt a burst read with a write command, burst stop command must be asserted to avoid data contention on the i/ o bus by placing the dq s (output drivers) in a high impedance state at least one clock cycle before the write command is initiated. read interrupted by burst stop & a write command < burst length=4, cas latency=2 > read a read b nop nop nop nop nop nop nop dqs dq s cas latency=2 dout a 0 dout a 1 dout b 0 dout b 1 dout b 2 dout b 3 command < burst length=4, cas latency=2 > read burst stop nop write nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 din 0 din 1 din 2 din 3 ck, ck ck, ck 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 nop
target 64m ddr sgram - 14 - KM432D2131 rev. 0.3 (may. 1999) a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precharge intervals without interrupting a read burst. a precharge command to output disable latency is equivalent to the cas latency. read interrupted by a precharge command < burst length=8, cas latency=2 > read nop precharge nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 a burst write can be interrupted before completion of the burst by the new write command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. when the previous burst is inter- rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro- grammed burst length is satisfied. write interrupted by a write command < burst length=4 > nop write a write b nop nop nop nop nop nop dqs dq s din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 1 tck interval ck, ck ck, ck 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 dout 4 dout 5 dout 6 dout 7 interrupted by precharge
target 64m ddr sgram - 15 - KM432D2131 rev. 0.3 (may. 1999) a burst write can be interrupted by a read command to any bank. the dq s must be in the high impedance state at least one clock cycle before interrupting read data appears on the outputs to avoid data contention. when the read com- mand is registered, any residual data from the burst write cycle will be masked by dm. the delay from the last data to read command (tcdlr) is required to avoid the data contention dram inside. write interrupted by a read & dm command < burst length=8, cas latency=2 > nop write nop nop read nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 a burst write operation can be interrupted before completion of the burst by a precharge of the same bank. a write recovery time(trdl) is required before a precharge command to finish the write operation. when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. write interrupted by a precharge & dm din 4 din 5 dout 0 dout 1 dout 2 command < burst length=8 > nop write a nop nop precharge nop nop nop write b dqs dq s dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dinb 0 dinb 1 dinb 2 dinb 3 dina 6 dina 7 din 6 din 7 t cdlrmin t rdlmin t dqssmax dqs dq s t cdlrmin t dqssmin din 0 din 1 din 2 din 3 din 4 din 5 din 6 din 7 d m dqs dq s t rdlmax t dqssmin dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dina 6 dina 7 d m dinb 0 dinb 1 dinb 2 dinb 3 t dqssmax dout 0 dout 1 dout 2 ck, ck ck, ck dout 3 dout 3 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 minimum tdqss maximum tdqss d m minimum tdqss maximum tdqss d m
target 64m ddr sgram - 16 - KM432D2131 rev. 0.3 (may. 1999) the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock only . the burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. when the burst stop command is issued during a burst read cycle, both the data and dqs(data strobe) go to a high impedance state after a delay which is equal to the cas latency set in the mode reg- ister. the burst stop command, however, is not supported during a write burst operation. burst stop command the ddr sgram has a data mask function that can be used in conjunction with data write cycle only, not read cycle. when the data mask is activated (dm high) during write operation the write data is masked immediately(dm to data-mask latency is zero). dm must be issued at the rising edge or the falling edge of data strobe instead of a clock edge. dm function command < burst length=4, cas latency=2, 3 > read a burst stop nop nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dqs dq s cas latency=3 command < burst length=8 > write nop nop nop nop nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 the burst ends after a delay equal to the cas latency. dout 0 dout 1 dm din 4 din 5 din 6 din7 masked by dm=h ck, ck ck, ck 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 t dqssmax
target 64m ddr sgram - 17 - KM432D2131 rev. 0.3 (may. 1999) the auto precharge command can be issued by having column address a 8 high when a read or a write command is asserted into the ddr sgram. if a 8 is low when read or write command is issued, then normal read or write burst oper- ation is asserted and the bank remains active after the completion of the burst sequence. when the auto precharge com- mand is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write cycle after t ras (min) is satisfied. auto-precharge operation command < burst length=4, cas latency=2, 3 > bank a nop read a nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 if a read with auto-precharge command is initiated, the ddr sgram automatically starts the precharge operation on bl/2 clock later from a read with auto-precharge command when t ras (min) is satisfied. if not, the start point of precharge operation will be delayed until t ras (min) is satisfied. once the precharge operation has started the bank cannot be reacti- vated and the new command can not be asserted until the precharge time( t rp ) has been satisfied. read with auto precharge active auto precharge * bank can be reactivated at the t rp completion of precharge begin auto-precharge dqs dq s cas latency=3 dout 0 dout 1 dout 2 dout 3 when the read with auto precharge command is issued, new command can be asserted at t3,t4 and t5 respectively as follows, even the new command for the same bank is illigal. asserted command for same bank for different bank 3 4 5 3 4 5 read interrupt read + no ap*1 read+ no ap illegal legal legal legal active illegal illegal fail legal legal legal precharge illegal illegal fail legal legal legal *1 : ap = auto precharge ck, ck 2 0 1 5 3 4 8 6 7
target 64m ddr sgram - 18 - KM432D2131 rev. 0.3 (may. 1999) if a 8 is high when write command is issued , the write with auto-precharge function is performed. any new command to the same bank should not be issued until the internal precharge is completed. the internal precharge begins after keeping t rdl (min). write with auto precharge command < burst length=4 > bank a nop write a nop nop nop nop nop nop dqs dq s din 0 din 1 din 2 active auto precharge * bank can be reactivated at completion of t rp t rdl t rp internal precharge start the precharge command is used to precharge or close a bank that has been activated. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of the clock, ck. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select addresses(ba 0 , ba 1 ) are used to define which bank is precharged when the command is initiated. for write cycle, t rdl (min.) must be satisfied from the start of the last burst write cycle until the precharge command can be issued. after t rp from the precharge, an active com- mand to the same bank can be initiated. precharge command < bank selection for precharge by bank address bits > a 8 /ap ba1 ba 0 precharge 0 0 0 bank a only 0 0 1 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks ck, ck < block write > ck, ck cmd t bpl t rp auto precharge starts bw 2 0 1 5 3 4 8 6 7 2 0 1 5 3 4 8 6 7 din 3
target 64m ddr sgram - 19 - KM432D2131 rev. 0.3 (may. 1999) command cke pre t rp t rc a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. after 1 clock cycle from the self refresh command, all of the external control signals including system clock(ck, ck ) can be dis- abled except cke. the clock is internally disabled during self refresh operation to reduce power. to exit the self refresh mode, supply stable clock input before returning cke high, assert deselect or nop command and then assert cke high. the auto refresh is required before self refresh entry and after self refresh exit. self refresh auto =high refresh cmd command cke stable clock t is auto refresh nop self refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock, ck. all banks must be precharged and idle for a t rp (min) before the auto refresh command is applied. no con- trol of the external address pins is required once this cycle has started because of the internal address counter. when the refresh cycle has completed, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc( min). auto refresh ck, ck ck, ck t rc(min) t is 2 0 1 5 3 4 8 6 7 11 9 10 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
target 64m ddr sgram - 20 - KM432D2131 rev. 0.3 (may. 1999) cke precharge active the power down is entered when cke low,and exited when cke high. once the power down mode is initiated, all of the receiver circuits except ck and cke are gated off to reduce power consumption. the both bank should be in idle state prior to entering the precharge power down mode and cke should be set high at least 1 tck+tis prior to row active com- mand. during power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(t ref ) of the device. power down mode power entry down precharge command ck, ck t is t is t is t is 2 0 1 5 3 4 8 6 7 12 10 11 13 14 9 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ power exit down precharge power entry down active power exit down active read (nop)
target 64m ddr sgram - 21 - KM432D2131 rev. 0.3 (may. 1999) simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dsf dm ba 0,1 a 8 /ap a 10 ,a 9 ,a 7 ~a 0 note register mode register set h x l l l l l x op code 1, 2 special mode register set h refresh auto refresh h h l l l h x x x 3 self refresh entry l 3 exit l h l h h h x x x 3 h x x x 3 bank active & row addr. h x l l h h x x v row address read & column address auto precharge disable h x l h l h x x v l column address 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l l x v l column address 4 auto precharge enable h 4, 6 block write & column address auto precharge disable h x l h l l h x v l column address 4, 5 auto precharge enable h 4,5,6,9 burst stop h x l h h l x x x 7 precharge bank selection h x l l h l x x v l x all banks x h 5 active power down entry h l h x x x x x x l v v v exit l h x x x x x x precharge power down mode entry h l h x x x x x x l h h h exit l h h x x x x x l h h h x dm h x v x 8 no operation command h x h x x x x x x l h h h 1. op code : operand code a 0 ~ a 10 & ba 0 ~ ba 1 : program keys. (@mrs) a 6 : lcr @ smrs/color register exists only one per dqi which all banks share. color is loaded into chip through dq pin 2. mrs can be issued only at all banks precharge state. smrs can be issued only if dq s are idle. a new command can be issued after 1 clock cycle of mrs/smrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. note :
target 64m ddr sgram - 22 - KM432D2131 rev. 0.3 (may. 1999) 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 8 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. graphic features are added to sdram s original features. if dsf is tied to low, graphic functions are disabled and chip operates as a 64m sdram with 32 dq s.
target 64m ddr sgram - 23 - KM432D2131 rev. 0.3 (may. 1999) function truth table current state cs ras cas we dsf address command action idle h x x x x x desel nop l h h h x x nop nop l h h l x x term nop l h l x x ba, ca, a 8 read/write/bw illegal*2 l l h h x ba, ra act bank active, latch ra l l h l x ba, a 8 pre/prea nop*4 l l l h x x refa auto-refresh*5 l l l l l op-code, mode-add mrs mode register set*5 h smrs special mode register set row active h x x x x x desel nop l h h h x x nop nop l h h l x x term nop l h l h x ba, ca, a 8 read/reada begin read, latch ca, determine auto-precharge l h l l l ba, ca, a 8 write/writea begin write, latch ca, determine auto-precharge l h l l h ba, ca, a 8 bw/bwa begin block write, latch ca, determine auto-precharge l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea precharge/precharge all l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs special mode register set read h x x x x x desel nop(continue burst to end) l h h h x x nop nop(continue burst to end) l h h l x x term terminate burst l h l h l ba, ca, a 8 read/reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l x ba, ca, a 8 write/writea bw/bwa illegal l l h h l ba, ra act illegal*2 l l h l l ba, a 8 pre/prea terminate burst, precharge l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal
target 64m ddr sgram - 24 - KM432D2131 rev. 0.3 (may. 1999) function truth table (continued) current state cs ras cas we dsf address command action write h x x x x x desel nop(continue burst end) l h h h x x nop nop(continue burst end) l h h l x x term illegal l h l h x ba, ca, a 8 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-precharge*3 l h l l l ba, ca, a 8 write/writea terminate burst, latch ca, begin new write, determine auto- precharge*3 l h l l h ba, ca, a 8 bw/bwa terminate burst , latch ca, new block write, determine ap. l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea terminate burst with dm=high, precharge l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal read with auto precharge h x x x x x desel nop(continue burst end) l h h h x x nop nop(continue burst end) l h h l x x term illegal l h l x x ba, ca, a 8 read/write illegal*2 l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea illegal*2 l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal write with auto recharge h x x x x x desel nop(continue burst to end) l h h h x x nop nop(continue burst to end) l h h l x x term illegal l h l x x ba, ca, a 8 read/write illegal*2 l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea illegal*2 l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal
target 64m ddr sgram - 25 - KM432D2131 rev. 0.3 (may. 1999) function truth table (continued) current state cs ras cas we dsf address command action block write recovering h x x x x x desel nop(continue block write) l h h h x x nop nop(continue block write) l h h l x x term nop l h l x x ba, ca, a 8 read/reada write/ writea illegal l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea terminate block write, pre- charge l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal pre- charging h x x x x x desel nop(idle after t rp ) l h h h x x nop nop(idle after t rp ) l h h l x x term nop l h l x x ba, ca, a 8 read/write illegal*2 l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea nop*4(idle after t rp ) l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal row activating h x x x x x desel nop(row active after t rcd ) l h h h x x nop nop(row active after t rcd ) l h h l x x term nop l h l x x ba, ca, a 8 read/write illegal*2 l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea illegal*2 l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal
target 64m ddr sgram - 26 - KM432D2131 rev. 0.3 (may. 1999) function truth table (continued) abbreviations : h=high level, l=low level, v=valid, x=don t care ba=bank address, ra=row address, ca=column address, nop=no operation note : 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. same bank s previous auto precharge will not be performed. but if bank is different, previous auto precharge will be performed. illegal = device operation and/or data-integrity are not guaranteed. current state cs ras cas we dsf address command action write recovering h x x x x x desel nop l h h h x x nop nop l h h l x x term nop l h l h x ba, ca, a 8 read illegal*2 l h l l l ba, ca, a 8 write/writea new write, determine ap. l h l l h ba, ca, a 8 bw/bwa new bw, determine ap. l l h h x ba, ra act illegal*2 l l h l x ba, a 8 pre/prea illegal*2 l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal re- freshing h x x x x x desel nop(idle after t rp ) l h h h x x nop nop(idle after t rp ) l h h l x x term nop l h l x x ba, ca, a 8 read/write illegal l l h h x ba, ra act illegal l l h l x ba, a 8 pre/prea illegal l l l h x x refa illegal l l l l l op-code, mode-add mrs illegal h smrs illegal
target 64m ddr sgram - 27 - KM432D2131 rev. 0.3 (may. 1999) function truth table for cke abbreviations : h=high level, l=low level, x=don t care note : 1. after cke s low to high transition to exist self refresh mode. and a time of trc(min) has to be elapse after cke s low to high transition to issue a new command. 2. cke low to high transition is asynchronous as if restarts internal clock. a minimum setup time "tss + one clock" must be satisfied before any command other than exit. 3. power-down and self refresh can be entered only from the all banks idle state. 4. must be a legal command. current state cke n-1 cke n cs ras cas we dsf add action self- refreshing h x x x x x x x invalid l h h x x x x x exit self-refresh*1 l h l h h h x x exit self-refresh*1 l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal l l x x x x x x nop(maintain self-refresh) both bank precharge power down h x x x x x x x invalid l h h x x x x x exit power down*2 l h l h h h x x exit power down*2 l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal l l x x x x x x nop(maintain power down) all banks idle h h x x x x x x refer to function true table h l h x x x x x enter power down*3 h l l h h h x x enter power down*3 h l l h h l x x illegal h l l h l x x x illegal h l l l h h l ra row (& bank) active h l l l l h l x enter self-refresh*3 h l l l l l l op code mode register access h l l l l l h op code special mode register access l x x x x x x x refer to current state=power down any state other than listed above h h x x x x x x refer to function true table h l x x x x x x begin clock suspend next cycle*4 l h x x x x x x exit clock suspend next cycle*4 l l x x x x x x maintain clock suspend
target 64m ddr sgram - 28 - KM432D2131 rev. 0.3 (may. 1999) read simplified state diagram self refresh auto refresh power down row active reada writea writea pre charge power on idle mode power down register set refs refsx refa mrs ckel ckeh act ckel ckeh write write writea pre pre power applied reada pre pre reada reada read read automatic sequence command sequence /bw /bwa /bw /bwa writea /bwa bst
target 64m ddr sgram - 29 - KM432D2131 rev. 0.3 (may. 1999) absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.6 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : power & dc operating conditions(sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) parameter symbol min typ max unit note device supply voltage v dd 3.135 3.3 3.465 v 1 output supply voltage v ddq 2.375 2.50 2.625 v 1 reference voltage v ref 1.15 1.25 1.35 v 2, 3 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 4 input logic high voltage v ih v ref +0.18 - v ddq +0.30 v input logic low voltage v il -0.30 - v ref -0.18 v 5 output logic high voltage v oh vtt+0.76 - - v i oh =-15.2ma output logic low voltage v ol - - vtt-0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 1. under all conditions v ddq must be less than or equal to v dd . 2. typically, the value of v ref is expected to be about 0.50*v ddq of the transmitting device. v ref is expected to track variation in v ddq . 3. peak to peak ac noise on v ref may not exceed 2% v ref (dc). 4. v tt of the transmitting device must track v ref of the receiving device. 5. v il (min.)= -1.5v ac(pulse width 5ns). 6. for any pin under test input of 0v v in v dd +0.3v is acceptable. for all other pins that are not under test v in =0v. note :
target 64m ddr sgram - 30 - KM432D2131 rev. 0.3 (may. 1999) ac characteristics simplified timing(1) @ bl=4, cl=2 parameter symbol -6 -7 -8 -10 unit note min max min max min max min max ck cycle time cl=2 t ck 12 1000 12 1000 12 1000 13 1000 ns cl=3 6 7 8 10 ns ck high level width t ch 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck low level width t cl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck rising edge to ck rising edge delay t ccb 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck edge to data strobe edge t acs 2.5 5.5 2.5 5.5 2.5 6.0 2.5 6.0 ns ck edge to output data edge t ac 2.5 5.5 2.5 5.5 2.5 6.0 2.5 6.0 ns data strobe edge to ouput data edge t dqsq -0.4 +0.4 -0.5 +0.5 -0.5 +0.5 -0.6 +0.6 ns data valid widow t dvq 1.9 2.1 2.6 3.3 ns data strobe valid window t dvqs 1.9 2.1 2.6 3.3 ns dqs low-z to 1st valid dqs(preamble) @ read t slz 4 8 5 9 6 10 8 12 ns last valid dqs to dqs hi-z(postamble) @ read t shz 4 8 5 9 6 10 8 12 ns last valid dqs to dqs hi-z(postamble) @ write t dshz 2 2.5 3 4 ns data out active to hi-z t hzq 3 3 3 3 ns dqs write preamble setup time t sdqs 0 0 0 0 ns ck to valid dqs-in t dqss 3.5 1 tck 4 1 tck 4 1 tck 4.5 1 tck ns dqs-in high level width t sih 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width t sil 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in cycle time t sic 1 1 1 1 tck input setup time t is 1.5 1.75 2 2.5 ns input hold time t ih 1 1 1 1 ns data in & dm set-up time t ds 0.4 0.4 0.4 0.6 ns data in & dm hold time t dh 0.7 0.7 0.8 1 ns ck transition time t t 0.5 1.5 0.5 1.7 0.5 2 0.5 2.5 ns 1 3 4 6 7 tccb tcl tck tacs hi-z hi-z ck, ck dqs dq cs dm 2 5 tis tih tac 8 tds tdh 0 1 qa0 tdqsq tshz tslz db0 db1 db2 db3 tdvqs tsic tdqss tsih tsil tds tdh thzq tch tdvq qa1 qa2 qa3 tsdqs tdshz command read write
target 64m ddr sgram - 31 - KM432D2131 rev. 0.3 (may. 1999) ac characteristics 1. note : when t dqss is close to the minimum value, t cdlr and t rdl are 2 tck ,3 tck , respectively. when t dqss is close to the maximum value, t cdlr and t rdl are 1.5 tck, 2.5 tck respectively. for normal write operation, even numbers of din are to be written inside dram. simplified timing(2) @ bl=4, cl=2 parameter symbol -6 -7 -8 -10 unit note min max min max min max min max row cycle time t rc 70 70 70 70 ns row active time t ras 48 100k 49 100k 48 100k 50 100k ns ras to cas delay t rcd 18 20 20 20 ns row precharge time t rp 18 21 20 20 ns row active to row active delay t rrd 12 14 16 20 ns last data in to row precharge t rdl 3.5 tck - t dqss 3.5 tck - t dqss 3.5 tck - t dqss 3.5 tck - t dqss ns 1 last data in to read command delay t cdlr 2.5 tck - t dqss 2.5 tck - t dqss 2.5 tck - t dqss 2.5 tck - t dqss ns 1 last data in to write command delay t cdlw 0 0 0 0 tck col. address to col. address delay t ccd 1 1 1 1 tck mode register set cycle time t mrd 1 1 1 1 tck special mode register set cycle time t smrd 1 1 1 1 tck block write cycle t bwc 1 1 1 1 tck block write to precharge t bpl 4 4 4 4 tck qa0 qa1 qa2 qa3 0 1 2 3 4 5 6 7 8 baa ra ra trcd active active write write qa0 qa1 qa2 qa3 qb0 qb1 qb3 13 14 15 16 17 18 19 20 21 baa bab ca cb tccd baa ca 9 10 11 12 prech baa 22 read baa ra ra qa0 qa1 qa2 qa3 normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) write interrupted by read (@ cl=2, bl=4) baa ra ra bab rb rb qb2 tcdlr tras trc trp trrd command dqs dq we dm ck, ck a8/ap addr (a0~a7, ba[1:0] a9,a10) active write
target 64m ddr sgram - 32 - KM432D2131 rev. 0.3 (may. 1999) dc characteristics note : 1. measured with outputs open. 2. refresh period is 16ms. 3. assumes minimum column address update cycle t bwc (min). parameter symbol test condition cas latency version unit note -6 -7 -8 -10 operating current (one bank active) i cc1 burst lenth=2 t rc 3 t rc (min) i ol =0ma 260 240 220 200 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc =10ns 2 ma i cc2 ps cke v il (max), ck v il (min), t cc = 2 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc =10ns input signals are changed once 65 ma i cc2 ns cke 3 v ih (min),ck v il (max), t cc = 20 active standby current power-down mode i cc3 p cke v il (max), t cc =10ns 4 ma i cc3 ps cke vil(max),ck vil(max), t cc = 4 active standby current in in non power-down mode i cc3 n cke 3 vih(min), cs 3 vih(min), t cc =10ns input signals are changed once 65 ma i cc3 ns cke 3 vih(min),ck vil(max), t cc = input signals are stable. 40 operating current (burst mode) i cc4 i ol =0ma page burst all banks activated t ccd =2 tck 3 400 360 320 280 ma 1 2 300 300 300 280 refresh current i cc5 t rc 3 t rc (min) 300 290 280 270 ma 2 self refresh current i cc6 cke 0.2v 2 ma operating current (one bank block write) i cc7 t cc 3 t cc (min) , i ol =0ma , t bwc (min) 420 380 340 300 ma 3 recommended operating conditions unless otherwise noted, t a =0 to 65 c)
target 64m ddr sgram - 33 - KM432D2131 rev. 0.3 (may. 1999) ac operating test conditions (v dd =3.3v 0.15v, t a = 0 to 65 c) parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il ) v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 capacitance (v dd =3.3v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance(a 0 ~a 10 , ba 0 ~ba 1 ) c in1 2.5 4.5 pf input capacitance ( ck, cke, cs , ras , cas , we ) c in2 2.5 5.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 ) c out 2.5 5.5 pf input capacitance(dm) c in3 2.5 5.5 pf r t =50 w output c load =30pf (fig. 1) output load circuit z0=50 w v ref =0.5*v ddq v tt =0.5*v ddq decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note :
target 64m ddr sgram - 34 - KM432D2131 rev. 0.3 (may. 1999) basic timing (setup, hold and access time @bl=4, cl=2) 1 3 4 6 7 t c c b t c l t c k t c h t c l t c k t a c s h i - z h i - z c k , c k c o m m a n d d q s d q c k e c s b a [ 1 : 0 ] a 8 / a p a d d r w e d m r a s c a s 2 5 ( a 0 ~ a 7 , a 9 , a 1 0 ) b a a b a b c a c b t i s t i h r e a d w r i t e t a c 8 h i g h t d s t d h 0 1 q a 0 t d q s q t s h z t s l z d b 0 d b 1 d b 2 d b 3 t d v q s t s i c t d q s s t s i h t s i l t d s t d h t h z q t c h t d v q q a 1 q a 2 q a 3 t s d q s t d s h z
target 64m ddr sgram - 35 - KM432D2131 rev. 0.3 (may. 1999) multi bank interleaving read (@bl=4, cl=2) a c t i v e a c t i v e r e a d r e a d q a 0 q a 1 q a 2 q a 3 q b 0 q b 1 q b 2 q b 3 c o m m a n d d q s d q 0 1 2 3 4 5 6 7 8 c k e c s w e d m r a s c a s b a a b a b b a a b a b r a r b r a r b c a c b t r r d t r c d h i g h t r c d t c c d t c a c c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 36 - KM432D2131 rev. 0.3 (may. 1999) multi bank interleaving write (@bl=4) c o m m a n d d q s d q c k e c s w e d m r a s c a s a c t i v e r a a c t i v e r b w r i t e c a b a a b a b b a a b a b r a h i g h r b c b d a 0 d a 1 d a 2 d a 3 d b 0 d b 1 d b 2 d b 3 t r r d t r c d t r c d t c c d c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ] w r i t e 0 1 2 3 4 5 6 7 8
target 64m ddr sgram - 37 - KM432D2131 rev. 0.3 (may. 1999) auto precharge after read burst (@bl=8) c o m m a n d c k e c s w e d m r a s c a s t r p r e a d a c t i v e q a 0 q a 1 q a 2 q a 3 q a 4 q a 5 q a 6 q a 7 n o t e 1 a u t o p r e c h a r g e s t a r t d q s ( c l = 3 ) d q ( c l = 3 ) b a a b a a c a r a r a h i g h n o t e 1 . t h e r o w a c t i v e c o m m a n d o f t h e p r e c h a r g e b a n k c a n b e i s s u e d a f t e r t r p f r o m t h i s p o i n t . t h e n e w r e a d c o m m a n d o f a n o t h e r a c t i v a t e d b a n k c a n b e i s s u e d f r o m t h i s p o i n t . a t b u r s t r e a d / w r i t e w i t h a u t o p r e c h a r g e , c a s i n t e r r u p t o f t h e s a m e b a n k i s i l l e g a l . d q s ( c l = 2 ) d q ( c l = 2 ) q a 0 q a 1 q a 2 q a 3 q a 4 q a 5 q a 6 q a 7 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ] 0 1 2 3 4 5 6 7 8
target 64m ddr sgram - 38 - KM432D2131 rev. 0.3 (may. 1999) c o m m a n d d q s d q 0 1 2 3 4 5 6 7 8 c k e c s w e d m r a s c a s t r p n o t e 1 a u t o p r e c h a r g e s t a r t b a a c a w r i t e a c t i v e h i g h n o t e 1 . t h e r o w a c t i v e c o m m a n d o f t h e p r e c h a r g e b a n k c a n b e i s s u e d a f t e r t r p f r o m t h i s p o i n t . t h e n e w r e a d / w r i t e c o m m a n d o f a n o t h e r a c t i v a t e d b a n k c a n b e i s s u e d f r o m t h i s p o i n t . a t b u r s t r e a d / w r i t e w i t h a u t o p r e c h a r g e , c a s i n t e r r u p t o f t h e s a m e b a n k i s i l l e g a l . t r d l b a a r a r a d a 0 d a 1 d a 2 d a 3 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ] auto precharge after write burst (@bl=4)
target 64m ddr sgram - 39 - KM432D2131 rev. 0.3 (may. 1999) normal write burst (@bl=4) c o m m a n d d q s d q c k e c s w e d m r a s c a s 0 1 2 3 4 5 6 7 8 t r d l b a a c a w r i t e p r e c h a r g e h i g h b a a d a 0 d a 1 d a 2 d a 3 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 40 - KM432D2131 rev. 0.3 (may. 1999) write interrupted by precharge & dm (@bl=8) c o m m a n d d q s d q c k e c s w e d m r a s c a s 0 1 2 3 4 5 6 7 8 w r i t e p r e w r i t e w r i t e t r d l t c c d b a a b a b c a c b c h a r g e h i g h b a c c c b a a d a 0 d a 1 d a 2 d a 3 d a 4 d a 5 d a 6 d a 7 d b 0 d b 1 d c 0 d c 1 d c 2 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 41 - KM432D2131 rev. 0.3 (may. 1999) write interrupted by a read (@bl=8, cl=2) c o m m a n d d q s d q c k e c s w e d m r a s c a s 0 1 2 3 4 5 6 7 8 w r i t e r e a d t c d l r m a s k e d b y d q m b a a b a b c b h i g h c a d a 0 d a 1 d a 2 d a 3 d a 4 d a 5 q b 0 q d b 1 q b 2 q b 3 q b 4 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ] q b 5
target 64m ddr sgram - 42 - KM432D2131 rev. 0.3 (may. 1999) read interrupted by precharge (@bl=8) 0 1 2 3 4 5 6 7 8 c o m m a n d c k e c s w e d m r a s c a s d q s ( c l = 3 ) d q ( c l = 3 ) q a 0 q a 1 q a 2 q a 3 q a 4 q a 5 2 . 5 c l k v a l i d 5 e a b a a c a r e a d p r e c h a r g e h i g h b a a d q s ( c l = 2 ) d q ( c l = 2 ) q a 0 q a 1 q a 2 q a 3 q a 4 q a 5 1 . 5 c l k v a l i d 3 e a c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 43 - KM432D2131 rev. 0.3 (may. 1999) read interrupted by burst stop & write (@bl=8, cl=2) c o m m a n d d q s d q c k e c s w e d m r a s c a s 0 1 2 3 4 5 6 7 8 r e a d w r i t e q a 0 q a 1 b a a c a h i g h b a b c b b u r s t s t o p q b 0 q d b 1 q b 2 q b 3 q b 4 q b 5 q b 6 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ] q b 7
target 64m ddr sgram - 44 - KM432D2131 rev. 0.3 (may. 1999) read interrupted by a read (@bl=8, cl=2) d q s d q c k e c s w e d m r a s c a s 0 1 2 3 4 5 6 7 8 q b 0 q b 1 q b 2 q b 3 q b 4 q b 5 q a 0 q a 1 q b 6 q b 7 t c c d c o m m a n d b a a b a b c a c b r e a d r e a d h i g h c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 45 - KM432D2131 rev. 0.3 (may. 1999) dm function (@bl=8) only for write c o m m a n d d q s ( c l = 2 ) d q ( c l = 2 ) 0 1 2 3 4 5 6 7 8 c k e c s w e d m r a s c a s w r i t e b a a c a h i g h d a 0 d a 1 d a 2 d a 3 d a 4 d a 5 d a 6 d a 7 c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) b a [ 1 : 0 ]
target 64m ddr sgram - 46 - KM432D2131 rev. 0.3 (may. 1999) power up sequence & auto refresh(cbr) d q s d q 0 1 2 3 4 5 6 7 8 c k e c s w e d m r a s c a s h i g h c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) h i g h - z p r e c h a r g e 1 s t a u t o r e f r e s h m o d e r e s i s t e r s e t c o m m a n d t r c h i g h - z a d d r e s s k e y a l l b a n k c o m m a n d 2 n d a u t o r e f r e s h c o m m a n d c o m m a n d a n y c o m m a n d m i n i m u m o f 2 r e f r e s h c y c l e s a r e r e q u i r e d i n p u t s m u s t b e s t a b l e f o r 2 0 0 u s t r c b a [ 1 : 0 ] h i g h t r p ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t m r d
target 64m ddr sgram - 47 - KM432D2131 rev. 0.3 (may. 1999) mode register set d q s ( c l = 2 ) d q ( c l = 2 ) 0 1 2 3 4 5 6 7 8 c k e c s w e d m r a s c a s h i g h c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) p r e c h a r g e m o d e r e s i s t e r s e t c o m m a n d h i g h - z a l l b a n k c o m m a n d a n y c o m m a n d t r p h i g h - z h i g h - z a d d r e s s k e y b a [ 1 : 0 ] t m r d
target 64m ddr sgram - 48 - KM432D2131 rev. 0.3 (may. 1999) block write cycle (with auto precharge) d s f d m 0 1 2 3 4 5 6 7 8 c k e c s w e d q r a s c a s h i g h c k , c k a 8 / a p a d d r ( a 0 ~ a 7 , a 9 , a 1 0 ) r o w a c t i v e ( a - b a n k ) b l o c k w r i t e ( a - b a n k ) b l o c k w r i t e w i t h a u t o p r e c h a r g e ( a - b a n k ) * n o t e : 1 . a t b l o c k w r i t e , c a 0 ~ 3 a r e i g n o r e d . d q s b a a r a a r a a b a b c a b b a a c a b b a [ 1 : 0 ] t b w c
target 64m ddr sgram - 49 - KM432D2131 rev. 0.3 (may. 1999) 0.825 0 . 5 7 5 0.65 0.13 max package dimensions (tqfp) dimensions in millimeters 0.10 max 0 ~ 7 17.20 0.20 14.00 0.10 23.20 0.20 1.00 0.10 1.20 max * 0.05 min 0.80 0.20 #1 0.09~0.20 #100 0.30 0.08 20.00 0.10

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